Thursday, November 3, 2011
Wednesday, November 2, 2011
Ground Bounce
Ground Bounce Definition
Ground bounce is usually seen on high density VLSI where insufficient precautions have been taken to supply a logic gate with a sufficiently low resistance connection (or sufficiently high capacitance) to ground. In this phenomenon, when the gate is turned on, enough current flows through the emitter-collector circuit that the silicon in the immediate vicinity of the emitter is pulled high, sometimes by several volts, thus raising the local ground, as perceived by the transistor, to a value significantly above true ground. Relative to this local ground, the BASE voltage can go negative, thus shutting off the transistor. As the excess local charge dissipates, the transistor turns back on, possibly causing a repeat of the phenomenon, sometimes up to a half-dozen bounces.
Ground bounce is one of the leading causes of "hung" or metastable gates in modern digital circuit design. This happens because the ground bounce puts the input of a flip flop effectively at voltage level that is neither a one or a zero at clock time, or causes untoward effects in the clock itself. A similar phenomenon may be seen on the collector side, called VCC sag, where VCC is pulled unnaturally low.
Ground Bounce defines a condition when a device's output {really a number of outputs} switches from High to Low and causes a voltage change on other pins.
"Ground Bounce is a voltage oscillation between the ground pin on a component package and the ground reference level on the component die. Essentially it is caused by a current
surge passing through the lead inductance of the package." , IDT.
The problem is cause by the large current flow through the ground pin which develops a voltage drop over the lead inductance. This voltage drop on the ground line creates two main problems; first it rises the chip off ground [0 volts] potential
which increases the devices input threshold level, and increases the voltage level on an output pin which is not switching. Because a quiet output is effected by the other switching outputs, this is also called Simultaneous Switching Noise. Ground Bounce is really an issue with loss of noise margin, and is sometimes also called Ground Bounce Noise. The faster the slew rate of the logic family, the worse the problem becomes.
Normally when the information is provided in the data sheet ground bounce is given as Volp [Voltage Output Low Pulse], or output ground bounce. Ground Bounce will be given as some maximum voltage pulse, or a peak voltage below some maximum value.
Ground Bounce Elimination
With Glue Logic, the ground pins may have been moved around to reduce the inductance. Older families of Glue Logic used the far side pins as power and ground. For example a 14-pin IC would use pin 14 for power and pin 7 as ground. Newer ICs moved the power and ground pins to the center pins of the IC [pins 3 and 12 in this example]
Using a Surface Mount Device [SMD] instead of a Through Hole device will reduce the lead inductance. Normally SMD components are smaller, their leads are closer together and have a lower lead inductance. Refer here for a list of SMD ICs.
For FPGA's with hundreds of possible output pins the situation may change, and it's more up to the designer to deal with the issue. In most cases only a small portion of an FPGAs pins are connected to a separate set or power and ground connections. Every dozen Input/Output [I/O] pins switch off their own power and ground pins. So any one group of switching pins does not effect any other group of pins.
Start a noise budget to determine if the ground bounce, rise in ground potential, effects the design [Noise Margin Calculation ]. The voltage developed over the ground lead is proportional to the rate of change in current, so the faster the logic family the worse the problem becomes: V = L * [di/dt]. The more outputs switching at the same time, the larger the current value, and greater voltage bounce. Ground Bounce also occurs when the outputs switch from a 0 to a 1 but to a much smaller degree.
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| Series Termination |
Series termination of the line is one method of reducing ground bounce [Trace Termination Methods ]. Series termination resistors slow the rate of change of the output, and so reduce the instantaneous current on the ground line. How ever placing series resistors on all the possible output lines may not be practical. Also Resistor Pull-Ups on the line cause the ground bounce voltage to increase. The pull-up resistor allows the load capacitor to charge to it's full value, so as the line switches maximum current is delivered back to the driver. When practical eliminate pull-up resistors on devices with an issue, use pull-down resistors or series resistors if possible. Reducing the loading on the driver also reduces ground bounce. Ground Bounce may also be called Ground Lift.
Design Pitfalls
Ground Bounce is easy to understand, but you have to know the condition could exist. Without realizing the condition may exist could lead to a circuit failure. A one bit error [bit bounce] could occur at any time, weeks after system testing, when enough bits change in the same direction and at the same time. Any possible random data pattern could cause a ground bounce and an uncontrolled bit change in any near-by data pin. The only real way to test for this is to send every possible bit pattern down the bus while watching all the other unused pins for a change.
There are a number of other Logic Hazards when designing digital circuits.
Simultaneous Switching Outputs
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| Switching Outputs vs. Propagation Delay |
In addition to causing ground bounce Simultaneous Switching outputs will also cause the propagation delay of the output to increase. The greater the number of outputs switching simultaneously the larger the increase in propagation delay. Note that the graph shows Number of Outputs Switching vs delta Change in propagation delay for the outputs. Five different IC packages are shown, including SSOP, TSSOP, TVSOP, and LFBGA. The green trace representing the LFBGA shows a larger increase in delta prop delay because the LFBGA contains 96-pin instead of the 48 pins of the other packages. Of course because the increase in prop delay is unintended it could also be considered noise. Graphic credit; TI.
Design Guidelines [from Altera]
1. Add decoupling capacitors for as many VCC/GND pairs as possible.
2. Place the decoupling capacitors as close as possible to the power and ground pins of the device.
3. Limit load capacitance by buffering loads with an external device, or by reducing the number of devices that drive the bus.
4. Eliminate sockets whenever possible.
5. Reduce the number of outputs that can switch simultaneously and/or distribute them evenly throughout the device.
6. Use multi-layer PCBs that provide separate VCC and ground planes.
7. Add appropriate resistors in series to each of the switching outputs to limit the current flow into each of the outputs.
8. Use surface mount capacitors to minimize the lead inductance.
9. Use low effective series resistance (ESR) capacitors.
10. Each GND pin/via should be connected to the ground plane individually.
11. Eliminate pull-up resistors or use pull-down resistors.
... "Some bus applications use pull-up resistors to create a default high value for the bus. These resistors cause the load capacitances to charge up to the maximum voltage. Consequently, the driving device produces a higher level of ground bounce..."
editor note; there were additional design guidelines listed from this source, but they only related to programmable devices and are not listed here.
Of course implementing some of these guidelines may not be possible, but they are guidelines and not design rules. For example it my not be possible to reduce the number of outputs switching at the same time, as an 8-pin bus driver IC may have all its outputs switching half of the time. Also, using the same bus driver example which would already be the buffer, there would be no way to reduce its load capacitance.
Acronyms Defined
LFBGA; Low-profile Fine-pitch Ball Grid Array
SSOP; Shrink Small-Outline Package
TSSOP; Thin Shrink Small-Outline Package
TVSOP; Thin Very Small-Outline Package
Volp; Voltage Output Low Peak
Additional IC Package Styles.
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